• Determinism, jitter and timed structures on RT
• Execution time of Dynamic Dispatch LVOOP vs. Cluster and SubVIs on Real-Time

A closer look to the influence of inlining and Dynamic Dispatch on execution times in real-time systems

The requirement for the application was to execute a Simulink model with a deterministic 20kHz rate (50µs loop iteration time). The loop needed to read values from FPGA I/O nodes, execute the model via Model Interface Toolkit (MIT), and write back new set values to FPGA I/O nodes.

The following results were measured with RTETT in LV2016 running on a PXI on Par Lap ETS 13.1:

• Inlining (3 of 5 VIs) makes for 30% performance hit:

  • ~50µs loop time with inlining vs. ~68µs loop time without
• Dynamic Dispatch (5 of 5 VIs) has a minimal hit of ~ 3-5 µs:

  • ~68µs loop time with not inlined static dispatch vs. ~ 72µs DD
• Measurement uncertainty (differences in identical runs that we could not account for) is around 1 - 2µs for a 50 - 80µs loop iteration time

Furthermore:

• There is no measurable difference between using two bundle nodes with 5 elements vs 1 bundle node with 10 elements when writing to a cluster
• There is no measurable difference between writing to a plain cluster and writing to the object (not using a write accessor VI, but the bundle node directly in a class method)