Briefly, “Peer-to-Peer Streaming” means a directed, high throughput data transfer between two FPGA targets in a system. On the low-level side, this is accomplished with the PCIe 3.0 backplane connections, which enables the high throughput, but also has some pitfalls.

• Introduction to Peer-to-Peer Streaming: https://www.ni.com/de-de/support/documentation/supplemental/10/an-introduction-to-peer-to-peer-streaming.html
• Peer to Peer(P2P) Streaming FAQ: https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z000000fzy4SAA
• NI Peer-to-Peer Streaming Help: https://zone.ni.com/reference/en-XX/help/372831C-01/

• In general, try to modularize the code and test the modules (the P2P-Streaming) for its own in the first step. If everything works as expected, integrate the modules and test it again in small steps. Because of the very long compilation times for FPGA code, this approach is essential.
• Do not set the size of the P2P-buffers too small. It can affect the transfer rate and can lead to broken streams. See the P2P-Streaming FAQ for further information.
• The reader side buffer should be greater than the writer side buffer.
• The reader side should process faster than the writer side (faster (SCTL) loop, or usage of the “Handshake” protocol).
• If the host system (RT) says the stream is enabled, this information is based only on the writer side. However, it's not guaranteed that the reader side is working, too. Check that the reader is receiving data.
• Get sure to only write to the P2P stream when it's enabled.
• To get the maximum throughput: read only if the reader-buffer is about 1/4 full and adequate dimensioned.

Credits to Julian Lange for a lot of tips.

LV2020 running on a PXI on Par Lap ETS 13.1 with two PXIe-7822R. Measurements courtesy Benjamin Hinrichs.

• Peer-to-peer streaming between two FPGA targets in a PXI system

  • FPGA-1 and FPGA-2 connected via PXI trigger line
  • FPGA-1 sets the trigger line to high
  • FPGA-2 reads this trigger line and sets boolean in stream to TRUE
  • FPGA-1 measures time between setting trigger line to high and receiving first TRUE bit via P2P
  • Latency constantly at ~6µs (~512 ticks at 80MHz)